Bumps are formed on a surface of a wafer having integrated circuits, such as LSIs. Such bumps constitute a part of interconnects of an integrated circuit, and serve as terminals for connection to a circuit of an external package substrate (or a circuit substrate). The bumps are generally disposed along a periphery of a semiconductor chip (or die), and are connected to an external circuit by gold wires according to a wire bonding method or by leads according to a TAB method.
With the recent progress toward higher integration and higher density of semiconductor devices, the number of bumps for connection to external circuits is increasing, giving rise to the necessity to form bumps over the entire area of the surface of a semiconductor chip. Further, the need for shorter interconnect spacing has led to the use of a method (flip chip method) which involves flipping a semiconductor chip having a large number of bumps formed on its surface, and connecting the bumps directly to a circuit substrate.
Gold, silver, copper, nickel, solder, indium, or an alloy species comprising at least one of these metals is used as a bump material. Of these bump materials, solder is electrically conductive and has a relatively low melting point, and thus can be melted to bond elements at a temperature that does not cause damage to an electrical interconnect material or a semiconductor material. Therefore, solder is widely used to connect electrodes of a semiconductor chip to electrodes of a package substrate.
Electroplating is widely employed as a method of forming bumps. A process of forming bumps on a surface of a wafer having integrated circuits is one of the most important processes in a final stage of manufacturing of a semiconductor device. It is to be noted in this regard that an integrated circuit is formed on a wafer through many manufacturing processes. Therefore, very high reliability is required for a bump forming process which is performed on a wafer that has passed all the preceding processes. With the progress toward smaller-sized semiconductor chips, the number of bumps for connection to external circuits is increasing and bumps themselves are becoming smaller-sized. Accordingly, a need exists to enhance the accuracy of positioning for bonding of a semiconductor chip to a circuit substrate such as a package substrate. In addition, there is a strong demand for no defect being produced in a bonding process in which bumps are melted and solidified.
Copper bumps are formed on a seed layer of a wafer which is electrically connected to integrated circuits. A resist having openings is formed on the seed layer, and copper is deposited by copper plating on the exposed surface of the seed layer in the openings to thereby form copper bumps. The seed layer comprises a barrier layer, e.g. composed of titanium, and a feed layer, e.g. composed of copper. The barrier layer serves to prevent diffusion of copper which is a bump metal, while the feed layer serves to feed electricity to the wafer for electroplating. Thus, besides the function as a feed film for electroplating, the seed layer functions as a metal film for preventing diffusion of copper which is a bump metal. After filling the openings of the resist with copper, the resist is removed, and then the copper bumps are subjected to reflow processing.
FIG. 13 is a cross-sectional view of a bump after the plating process and before the reflow process. A bump height H is a distance from a bottom to a top of a bump 1. When the bump 1 is formed by plating in an opening of a resist, a dome 2 is formed at the top portion of the bump 1. This dome 2 is the top portion having an inwardly curved side surface. In FIG. 13, a dome height is represented by dh. The bump height H is preferably not less than 10 μm in order to ensure a uniform height of bumps bonded to a circuit substrate.
In a semiconductor device manufacturing process which involves formation of TSVs, a via-middle metal exposing technique which comprises polishing and planarizing an entire surface of a wafer, containing head portions of vias formed by copper plating, with a CMP apparatus before performing reflow processing, and then performing chemical etching to expose the head portions of the vias, followed by the production of bumps, has recently been proposed under development of a 2.5-dimensional packaging technology (Seiichi Denda, “Higher-Dimensional Semiconductor Technology, 3D/2.5D/2.1D Packaging Using Through-Silicon Vias”, Tokyo Denki University Press, pp. 16-18).
It has recently been found through studies of such a packaging technology that a height of a via head, i.e. the dome height dh of a copper bump formed by plating, is preferably made as low as possible. If the dome height dh of the bump is low, a time required for a polishing process, which is to be performed after plating, can be shortened. However, the dome height dh depends largely on the bump height H; therefore, it is difficult to control the dome height dh independently of the bump height H. Further, the required dome height dh may vary depending on conditions of subsequent processing. Under such a situation, there is a demand for a technique which can control the dome height dh without depending on the bump height H.